Circuit for performing multiplication by character selection utilizing a pair of unijunction transistors

ABSTRACT

A CIRCUIT FOR PERFORMING MULTIPLICATION IS DISCLOSED WHEREIN CIRCUITRY IS PROVIDED FOR CONTROLLING THE MULTIPLICATION OF THE NUMERICAL DATA IN PRESELECTED GROUPINGS.

United States Patent [72] Inventors Robert M. Henderson 5 Refe n s Ci d Williams Bay; UNlTED STATES PATENTS u a? 3,449,553 6/1969 Swan... 235 150.52 2,986,728 /1961 Hinckley ..235/l50.52UX 3,146,343 8/1964 Young 235 o.s2x [22] Filed Aug. 8, 1966 3,194,950 7/1965 Walls et al. 235/150.5X- Patented June 28, 197I [73] Assignee Fairbanks Morse Inc. 3,284,929 11/1966 Azure, Jr.... 307/284X New York NY 3,332,074 7/1967 Arnold 307/284X 3,408,509 10/1968 Mehaus... 307/305X 3,414,739 12/1968 Paidosh 307/301X [54] CIRCUIT FOR PERFORMING MULTIPLICATION Primary Examiner Malcolm A Morrison BY CHARACTER SELECTION UTILIZING A PAIR Assistant Examiner joseph F. gg OF UFUUNCTIOIF TR ANSISTORS Attorney-Petherbridge, O'Neill and Lindgren 9 Claims, 10 Drawing Flgs.

[52] U.S.Cl ..235/1S0.52, 235/1505, 307/283 [51] Int.Cl G06g 7/16, G06j 1/00 Field of Search 235/ 150.5, ABSTRACT: A circuit for performing multiplication is dis- 150.5l, 150.52, 150.53, 150.3, 150.31, 150.4; closed wherein circuitry is provided for controlling the mul- 307/283, 284, 301 305, 229, 230 tiplication of the numerical data in preselected groupings.

l l l 7 //5 a //6a 25 L/ I /97 g l l i 1 204 205 2590 //5/ CONTROL PATENTED JUH28 I97! SHEET 3 BF 6 E J E CIRCUIT FOR PERFORMING MULTIPLICATION BY CHARACTER SELECTION UTILIZING A PAIR OF UNIJUNCTION TRANSISTORS The present invention relates to electronic circuits for performing arithmetic operations such as multiplication and, more particularly, to an electronic circuit for performing multiplication by character selection.

In the copending application entitled Electronic Multiplying and Dividing Circuitry, U.S. Ser. No. 570,909, of Robert M. Henderson and Richard Zechlin filed on Aug. 8, I966, assigned to the same assignee as the present invention, circuits are disclosed for performing arithmetic multiplication and/or division. In some cases, it may be desirable to perform multiplication of selected factors at a higher speed and with even greater accuracy than can be obtained utilizing the circuit of said application Ser. No. 570,909.

Accordingly, it is a principal object of the present invention to provide improved circuits for multiplying selected factors at an increased rate of speed and with a high degree of accuracy.

It is another object of the present invention to provide electronic circuits for performing multiplication wherein the multiplication steps are selectively programmed.

It is another object of the present invention to provide a circuit for multiplying wherein the characters to be multiplied are arranged in groups and coupled to an output circuit in predetermined order position.

It is still another object of the present invention to provide a circuit for multiplying selected factors wherein absolute accuracy is obtained.

It is another object of the present invention to provide a circuit for multiplying wherein the operation of the circuit is timed and synchronized.

It is yet another object of the present invention to provide an improved circuit for multiplying wherein the operation of the circuit, once initiated, automatically proceeds through the remainder of the arithmetic operation.

In the attainment of the foregoing objects, there is provided a circuit for effecting multiplication by character selection wherein the factors to be multiplied are selected and, further, the resultant of each multiplication operation is positioned in selected numerical order when coupled to the associated counting circuit.

The circuit of the invention provides means for timing and synchronizing the operation of the circuit to assure maximum accuracy.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

FIGS. IA, 18, 1C and 1D show a schematic diagram of a multiplying circuit in accordance with the invention;

FIG. 1E shows the respective orientation of FIGS. 1A, 1B, 1C and ID;

FIG. 2 shows a graph useful in explaining the timing operation of the circuit;

FIG. 3 shows waveforms useful synchronizing operation of the circuit;

FIG. 4 shows a circuit which may be used in a portion of the circuit of FIG. IA;

FIG. 5 shows another circuit which may be used in a portion of the circuit of FIG. IA; and

FIG. 6 shows voltage waveforms useful in explaining the operation of the circuit ofFlGS. 4 and 5.

Refer now to FIGS. 1A, 1B, 1C and 1D.

The circuit of the invention for performing multiplication by character selection is shown in FIGS. 1A, 1B, 1C and ID. As mentioned, the circuit of FIG. 1A shows the multiplication portion of the overall circuit; the circuits of FIGS. 18 and 1C show the control or transfer register portion of the circuit; FIG. 1D shows the data input portion of the circuitry; and FIG. IE shows how the various FIGS. 1A,1B, and 1C and ID are oriented with respect to one another to show a schematic diagram of the overall circuit.

in explaining the THEORY OF MULTIPLICATION OPERATION Before explaining the overall operation of the multiplication by character selection in accordance with the invention, it may be advisable to briefly review the theory of operation of the basic multiplying circuitry as shown in FIGS. IA-lD herein and as more fully disclosed in the aforementioned copending application of Henderson et al., Ser. No. 570,909.

Referring to FIG. 1A of the present application, one embodiment of the basic multiplying unit disclosed provides a means of multiplying two input factors to obtain a product or resultant, and comprises a pair of unijunction transistors 62 and 52 and the associated capacitive and restive circuitry. For purposes of this brief explanation, assume that the emitter e of the unijunction transistor 62 is connected through a resistor K2 to a source of positive potential and to the upper plate ofa capacitor Kl (as oriented in FIG. IA). Assume the base tb2 of unijunction transistor 62 provides an output signal through lead K3. The base lbl of unijunction transistor 62 is connected through a resistor 121 to ground reference, as shown.

For purposes of this explanation, further assume the circuitry of unijunction transistor 52 is as follows. The base tbl is connected to ground reference and base tb2 provides an output through lead K5. The emitter e of unijunction transistor 52 is connected through a capacitor C1 to ground reference; and, the capacitor CI is connected in series with a variable resistor K4 to a positive potential. Note that the connections indicated as Kl-KS are all assumed connections; i.e., connections merely shown herein for purposes of explaining the basic theory of the circuit, and connections Kl-KS need not be used in the operating circuit of FIG. 1B.

The unijunction transistor 62 provides the time parameter for the circuit comprising one or more selected unit values of time and the unijunction transistor 52 provides a pulse output or count parameter which is representative of the product of the multiplication of two input factors. Assume that, in this example, for each unit value of time provided by unijunction transistor 62, the count unijunction transistor 52 will provide up to nine pulses.

Assume first that the capacitor K1 is adjusted such that it takes one unit value of time to charge capacitor Kl through resistor K2 to the avalanche point ofunijunction transistor 62. When unijunction transistor 62 avalanches; that is, conducts, KI will discharge through the emitter e to the base tbI circuit of unijunction transistor 62, and an output will be obtained at output lead K3. Assume the output at K3 is suitably connected to terminate a given multiplication operation.

Concurrently, as the capacitor K1 is being charged, the count capacitor C1 is also being charged through the associated resistor K4. The setting of K4 will determine the length of time it takes capacitor C1 to be charged to the avalanche point of unijunction transistor 52. When unijunction transistor 52 tires and conducts, capacitor C1 discharges through the emitter e to base tbl of unijunction transistor 52. The unijunction transistor 52 will thus provide an output pulse at its base tb2. Thus, it can be seen that if the capacitor K1 is arranged to provide a time value or base of one, and the resistor K4 is arranged to permit capacitor C1 to charge to the avalanche point of unijunction transistor 52 twice per unit length of time, then the unijunction transistor 52 will provide a total of two output pulses on lead 52 during this multiplication operation.

If capacitor K1 is varied to provide a time base of 9 unit lengths of time representative of an input factor nine, and K4 is varied to permit capacitor CI to charge to the avalanche point of unijunction transistor 52 six times during each unit length of time; that is, to be representative of an input factor of six. Accordingly, during the 9 unit length of time provided by capacitor K1 and unijunction transistor 62, the count unijunction transistor 52 will provide a total of 54 output pulses at lead K5. Thus, in the example, the output from the count unijunction transistor 52 is a multiplication which provides a product representative of the respective factors inserted as capacitive values 1(1 and resistive values K4.

As mentioned above, the dotted components indicated K1, K2, K3, K4 and K5 are all assumed components included in the circuitry for purposes of this brief explanation of the operation of the circuit of FIG. 1A. As also mentioned previously, a full description of the operation of the basic multiplication circuitry is provided in copending application Ser. No. 570,909.

SYNCHRONIZING CIRCUITS FIG. 1A includes a circuit portion labeled 200 for synchronizing the operation of the multiplying circuit to thereby assure that the proper resultant is obtained. More explicitly, the circuit portion 200 synchronizes the start ofa multiplication operation and the charging cycle of capacitors C1 and the capacitors associated with unijunction transistor 62, as will be explained. Further, the circuit portion 200 assures that the charge on capacitor C1 and the charge on the capacitors associated with unijunction transistor 62 are reduced to zero after the completion ofa multiplication operation and before initiating a succeeding multiplication operation.

The circuit 208 includes a monostable flip-flop circuit 192 including NPN transistors 185 and 186; a synchronizing unijunction transistor 187, and an NPN transistor 188. Transistors 185, 186 and 188 each have the usual emitter e, collector c and base b electrodes, and the unijunction transistor 187 includes the usual emitter e and two base elec' trodes [b1 and'tb2.

The base tb1 of unijunction transistor 62 is connected through a resistor 1911 to the base of transistor 185, and base tbll of transistor 62 is also connected through resistor 121 to ground reference. The base b of transistor 185 is connected through a resistor 194 and a capacitor 193 to the collector c of transistor 186. The emitter e of transistor 186 is connected to ground. The collector c of transistor 185 is also connected to base b of the second transistor 186 through resistor 198 of the monostable flip-flop circuit 192. The base b of transistor 186 is further connected through bias resistor 199 to ground. The emitter e of transistor 186 is connected to ground and its collector c is also connected through a resistor 228 to 30 volt potential. The collector c of transistor 185 is further connectcd to a junction or control terminal point 201 for purposes to be described.

The emitter e of unijunction transistor 62 is connected through lead 115a (FIG. 1A) and lead 1155b (FIG. 1D) to the time capacitors b1...b9 (FIG. 1D). The emitter e is further connected through a diode 202 to terminal point 201 (FIG. 1A). Terminal point 201 is further connected through a diode 21M, lead 205 to the emitter e of unijunction transistor 52. Terminal 201 is also connected through a diode 208 to the emitter e of the synchronizing unijunction transistor 187. The emitter e of unijunction transistor 187 is connected through a capacitor 213 to ground and through resistor 2143 to +30 volt potential. A resistor 203 is connected in parallel with capacitor 213 to permit fine adjustment of the timing cycle of unijunction transistor 187. The base tb2 of unijunction transistor 187 is connected through a resistor 219 to +30 volt potential and the base tb1 of unijunction transistor 187 is connectcd through a resistor 215 to ground.

The base lb1 of unijunction transistor 187 is connected to couple a positive signal through a diode 230 to the base b of the transistor 188. The base b of transistor 188 is connected through a resistor 216 to ground. Base b of transistor 188 is further connected through a resistor 217 and lead 151 to the zero control circuit. As will be more specifically described hereinbelow, energization of the zero control lead 151 causes 1 transistor 188 to conduct and disables or prevents the capacitor C1 from charging, and hence is effective to multiply by zero.

The emitter e of transistor 188 is connected through diode 2211 to ground and through a resistor 218 to 13+ potential. The

collector c of transistor 188 is connected through diode 219 and resistor 221 to the base tb2 of unijunction transistor 62 for purposes to be explained. The collector c of transistor 188 is connected through diode 223 to the emitter e of unijunction transistor 52 and to the one terminal of the count capacitor C1. The other terminal of capacitor C1 is connected to ground. The base lb! of unijunction transistor 52 is connected to ground, and its base lb2 is connected through leads 118a and 118 (see FIG. lB,C) to each ofthe cathodes of diodes 96, 106 and 129 associated with the output leads 89, 107 and 130, respectively, for purposes to be explained.

OPERATION OF SYNCHRONIZING CIRCUITS The monostable flip-flop circuit 192 of FIG. 1A including transistors and 186 provides a time delay between one multiplication and a succeeding multiplication so that a multiplication will not be initiated until the preceding multiplication is fully terminated. This is necessary since there is a measurable time required to permit the commutation or stepping of the transfer control registers of FIGS. 18 and 1C, to be explained hereinbelow.

Thus, the synchronizing circuit assures that the capacitors C1 and the capacitors b1...b9 (FIG. 1D) associated with unijunction transistor 62, as will be explained, are effectively discharged before each multiplication is initiated, and the synchronizing circuits further provide the basic unit value of time as will now be explained.

As mentioned, the monostable flip-flop 192 does not permit the next operation to proceed until a preset time elapses. When unijunction transistor 62 fires indicating the termination of a given time period, a positive potential is applied to the base b of transistor 185 of monostable multivibrator 192 turning transistor 185 ON, thus causing its collector c and terminal point 281 to drop essentially ground potential. The capacitors b1...b9 (FIG. 1D), the count capacitor C1 (FIG. IA), and the synchronizing capacitor 213 (FIG. 1A) which provides the unit value of time are all connected through respective diodes 202, 204 and 208 to terminal point 281. Hence, the aforementioned capacitors cannot charge until transistor 185 is turned OFF which occurs when monostable multivibrator 192 returns to its stable position with transistor 185 OFF and transistor 186 ON. As is known, the size of capacitor 193 and its charging rate determine the time delay; that is, the time required by monostable vibrator 192 to return from its unstable to its stable condition.

When transistor 185 turns OFF, the capacitors b1...b9 (FIG. 1D) and capacitor C1 start to charge toward the avalanche point of the unijunction transistors 62 and 52, respectively, to provide the time and count parameters for the circuit as described above.

Also, .when transistor 185 turns OFF, capacitor 213 starts to charge to the avalanche point of unijunction transistor 187. Capacitor 213 and the associated circuitry, including resistor 214, is precisely adjusted such that unijunction transistor 187 is caused to tire each selected or basic unit value of time. Each time unijunction transistor 187 fires, a pulse is provided from its base tb1 through diode 230 to the base b of transistor 188 to cause transistor 188 to turn ON. When transistor 188 turns ON, a discharge path for capacitor C1 is provided from the upper plate of capacitor C1, through diode 223, the conducting transistor 188, and diode 220 to ground. Thus, at the termination of each basic unit value of time, capacitor C1 is fully discharged. Unijunction transistor 187 continues to charge and discharge once for each unit value of time and synchronizes the count unijunction transistor 52 to the basic unit value of time. Thus, the parameters of capacitor 213, the unijunction transistor 187, and the circuitry associated therewith are selected to correspond to, or provide, a time base equal to the transistor unit value of time as is established by the circuitry associated with the count unijunction transistor 52,

The circuit is thus arranged so that the capacitor C1, the count capacitor, will start charging from the same initial level at the start of each unit value of time. Capacitor C1 charges and discharges once to represent a count in response to a signal applied thereto, and capacitor C1 can charge and discharge one or more times during each unit value of time.

Assume the condition of FIG. 2 which shows the multiplication of (A2)(A1)X(B2)(B1)=2IX29, and that the factors (A2)(A1) provide the count parameter and the factors (B2)(B1) provide the time parameter. In this condition and as will be explained more fully hereinafter; the count capacitor C1 is charged from the B+ line (FIG. 1D), resistor 01, diode 134a, lead 117 (FIGS. 1C, 13) to lead 117a, to capacitor C1 (FIG. IA). The resistor 01 has a resistance corresponding to the number 1. Accordingly, the capacitor C1 will be charged and discharged through its associated unijunction transistor 52 only one time before capacitor 213 charges to the avalanche point of synchronizing unijunction transistor 187. When unijunction transistor l87fires, transistor 188 is turned ON and completes the discharge path for capacitor C1 through transistor 188 as previously traced. Capacitor b9 representing the number 9 is charged from the B+ line (FIG. 18) through a conducting SCR and associated diode, line 64, resistor 63 (FIG. 1C), lead 115 to lead 115!) (FIG. 1D), capacitor b9 and conducting transistor S9 to ground. Note that lead 1151; (FIG. 1D) is connected through lead 115a (FIG. 1A) to the emitter e of unijunction transistor 62. The components are chosen so that the time required for capacitor b9 to charge to the avalanche point of its associated unijunction transistor 62 is equal to 9 unit values of time, at the end of these 9 unit values of time, unijunction transistor 62 is caused to fire. During the 9 unit values of time capacitor C1 fires a total of nine times; i.e., one time during each unit value oftime to provide a 1X9 multiplication. When unijunction transistor 62 fires, a signal is developed to shift the control registers to stop the multiplication of the first group of factors; i.e., IX9, and initiates the multiplication of a second group of factors, as will be explained.

The signal from unijunction transistor 62 is also coupled from its base tb1 through resistor 190 to base b of transistor 185 of monostable multivibrator 192 to cause the multivibrator to change to its unstable state, with transistor 185 ON and transistor 186 OFF. With transistor 185 ON its collector c and hence terminal 201 are essentially at ground potential. Accordingly, capacitors b1...b9, 213 and C1 cannot charge unit multivibrator 192 returns to its stable state with transistor I85 OFF and transistor 186 ON.

As mentioned, at the termination of each unit value of time, when transistor 188 conducts the potential at its collector drops. This drop in potential, as indicated by the negative excursions or blips of FIG. 3, is communicated through the circuit previously traced form the collector c of transistor 188 to the base tb2 of unijunction transistor 62. As is known, the avalanche point of a unijunction transistor is a function of the voltage differential between the base [b2 and the base [171. Thus, in view of the inherent exponential rise of the charge on capacitors b1...b9 and the flatness of the waveforms as the capacitors b1...b9 tend to become fully charged, the firing point of the unijunction transistor 62 might vary slightly. However, the negative excursions provided to base 1122 of transistor 62 will provide an exact timing point by providing a discrete voltage change between base !b2 and base tbl at precisely each basic unit value of time which will cause unijunction transistor 62 to fire at precisely the right instant.

TRANSFER CONTROL REGISTERS The transfer control registers for controlling, commutating or stepping the multiplying operation of the multiplying circuit portion of FIG. 1A from one selected grouping of input data to succeeding groupings of input data comprise a plurality of silicon controlled rectifiers labeled 13-17 and the associated circuitry shown in FIGS. 18 and 1C. For purposes of further description, the silicon controlled rectifiers will be referred to as SCRs, as is well-known in the art.

For purposes of describing the invention, the following multiplication has-been assumed:

where A and A, are the tens and units factors, respectively, in the multiplicand, and B and B are the tens and units factors, respectively, in the multiplier. Mathematically, the multiplication of the terms (A A,)X( I? B,) can be expressed as follows: g M) (B2B!)=(A1XB1)+(A2BIXIO)+(AIB2XIO)+AZB2 XI OX IO) I As an example, the foregoing relation can be represented by replacing the assumed letters by assumed numbers: (Zl) (29 )=(I 9)+(2OX9)+( IX20)+(2OX20) (2) As indicated above, the first operation consists of multiplying factors A1 by factors Bl; i.e., 1X9; the second operation consists of multiplying factors A2 by factor 81, etc., as shown in FIG. 2. The total time requiredto perform the multiplication assuming the unit time is microseconds is indicated in FIG. 2.

The transfer control registers are connected such that when one SCR turns ON it will enable the first two selected factors A1, B1 to multiplied. When that multiplication is completed a signal is provided to turn on the succeeding SCR to enable the next two factors, A2, B1, to be multiplied. The operation will continue until the complete multiplication of all the factors is performed.

The circuits of the transfer control registers will now be explained, with reference to FIGS. 18 and 1C. The transfer control registers comprising SCRs 13-17 and the associated circuitry are connected by a switch 12 across a suitable source of direct current potential indicated as a battery 11. The positive terminal of the battery is indicated as B+ (here being +30 volts), the negative terminal is indicated as B", and ground reference is indicated by the conventional symbol as is common practice in the art. 8- is shown as l0 volts DC.

The multiplication operation is initiated by momentarily closing a pushbutton switch 18 which energizes the circuit and then returns to its open position, as shown in FIG. 1C. When the pushbutton 18 is closed, an electrical circuit is completed to cause an NPN transistor 19 to conduct. Transistor 19 has a base b, and emitter e and a collector c. The base b of transistor 19 is connected through a resistor 26, start button 18 and switch 12 to the B+ terminal of the battery; base b is also connected through a biasing resistor 20 to ground reference. The emitter e of transistor 19 is connected to ground reference; its collector c is connected through a resistor 23, the primary winding W1 of the transformer 24 to lead 21, and switch 12 to the B+ terminal. Thus, when transistor 19 is caused to conduct a current path is completed from the B+ terminal through the primary winding W1, resistor 23, and the collector c to emitter e circuit of transistor 19 to ground. Note also that the collector c of transistor 19 is connected through a lead 22 to provide a signal which resets or presets the associated counters 300 to zero when a start signal is entered in the circuit, for purposes of clearing the counters before each multiplication operation.

The first SCR 13 in the transfer control register includes an anode a connected to the lead 21, a cathode 0 connected through a resistor 25 to ground reference and a gate electrode 3 connected to one terminal of the secondary winding W2 of transformer 24. The other terminal W2 is connected to cathode c of SCR 13; winding W2 is thus connected across the gate to cathode electrodes of SCR 13. A resistor is connected in parallel with winding W2.

The cathode c of SCR 13 is connected in common to the anodes of a bank of diodes 30-34. The anodes and cathodes of diodes 30-34 are not numbered but are respectively indicated by the symbols conventional in the art. The cathode of each of diodes 30-34 is connected to different portions of the circuit as will be described hereinbelow.

The cathode of SCR 13 is also connected through a series circuit including resistor 36, a diode 37 and a capacitor 38 to the cathode of the succeeding SCR (SCR 14) in the transfer control register. A resistor 39 is connected in parallel with resistor 36 and diode '37, for purposes which will become clear hereinbelow.

The cathode c of SCR 13 is further connected to a lead 40 as an input to the Rest Control SCR 17, FIG. 13, as will also be described hereinbelow.

The succeeding SCR in the transfer control register, SCR 14, likewise includesan anode a connected to lead 21, a gate electrode g connected to one terminal of a transformer winding TA and a cathode c connected through a resistor 41 to ground reference. The other terminal of winding TlOA is connected to the cathode c, and a resistor 140 is connected in parallel to winding T10A. The cathode c of SCR 14 is also connected in common to the anode of a bank of diodes 70- -74. The cathode of each of the diodes 70-74 is connected to different portions of the circuit as will be described hereinbelow. The cathode c of SCR 14 is further connected through a series circuit including a resistor 42, a diode 43 and a capacitor 44 to the cathode c of the succeeding SCR (SCR in the transfer control register. A resistor 45 is connected in parallel with resistor 42 and diode 43.

As will be appreciated from the foregoing description and from the drawings, FIGS. 18 and 1C, the circuits of SCR 13 and SCR 14 are similar. Likewise, the circuits of SCR l5 and SCR 16 are almost identical to the circuit of SCR 14. The circuit connections of SCR 15 and 16 will, accordingly, only be described in connection with the circuit operation as required. The circuit of SCR 17 is similar to the circuit of SCR 14 and includes additional circuitry as will be described.

Note that any number of SCRs similar to SCRs 14, 15 and 16 could be connected to function in the transfer control registers dependent on the groupings of the factors to be multiplied. 1n the multiplication of the factors (A2, AI) (B2,X B1) as described herein, four SCRs plus the Rest Control SCR 17 are employed. If, for example, the multiplication to be performed is that of (A4 A3, A2 A1) (B2 B1), a total of eight SCRs plus the Rest Control SCR 17 would be employed to control the multiplication in groupings such as (A1 B1), (A2 B1), (A3 B1), (A4 B1), (A1 B2), (A2 B2), (A3 B2) and (A4 B2).

REST CONTROL SCR 17 and the associated circuitry now to be described comprise a Rest Control or Rest circuit for the transfer control register of FIGS. 13 and 1C. The Rest Control SCR 17 is arranged to be energized each time a given multiplication operation is completed and the circuit is in condition for accepting additional data for initiating succeeding multiplication operation; i.e., the circuit is at rest and in condition to start the next operation.

The circuit of SCR 17 is similar to the circuits of the other SCRs 13-16, with the exception that the cathode c of SCR 17 is not connected to a bank of diodes; and, in addition, the circuit of SCR 17 includes an associated PNP type transistor 50 and Zener diode 51 for initially activating SCR 17 as follows.

Note that a capacitor 55 is similarly connected to SCR 17 as capacitor 38 is connected to SCR 13; and, capacitor 55 completes an electrical loop for the transfer control registers of FIGS. 1B and 1C through the lead 40 which is connected to the cathode c of SCR 13. The capacitor 55 functions similarly as capacitor 38 in a manner to be described.

The Rest Control circuit of SCR 17 includes the transistor 50 which comprises an emitter e, a base b and a collector cv The emitter e of transistor 50 is connected through the Zener diode 51 to lead 21 and the 13+ potential. As is known in the art, the cathode of the Zener diode 51 is connected to the positive potential and its anode is connected to the emitter e of transistor 50 to provide a voltage limiting function. The emitter e of transistor 50 is also connected through resistor 155 to ground reference, and its base I; is connected through resistor 53 to ground reference..The base b of transistor 50 is further connected to the cathodes of each of diodes 57 and 58 whose anodes are connected to respective leads B1 and B2 for purposes to be described. The collector c of transistor 51) is connected to the anode of a diode 54 whose cathode is connected to the gate electrode g of SCR 17.

The operation of the Rest Control circuit is as follows. When the switch 12 connected to the battery 11 is closed, the B+ potential will be coupled through lead 21 to the Zener diode 51 which breaks down and conducts. When the Zener diode 51 conducts, transistor 50 which was previously turned OFF will be biased-to conduct. The emitter e to collector 0 current in transistor 50 will flow from the collector c of transistor 50 through the diode 54, and the gate g to cathode c to electrode of SCR 17 causing SCR 17 to turn ON. When SCR 17 turns on, the potential at cathode c of SCR 17 will rise to a high level and this high potential will be coupled through diode 56 to base b of transistor 50 to turn transistor 56 OFF. The transfer control circuit of FIGS. 18 and 1C will now be in a condition to initiate a multiplication operation with SCR 17 turned ON and the other SCRs 13-16 turned OFF. I

Transistor 50 and Zener diode 51 have no function in the circuit other than to initially turn SCR 17 ON. Once SCR 17 is turned ON, or any of the other SCRs 13-16 are ON, transistor 50 is maintained in an OFF condition either by the potential applied through cathode c of SCR 17, or by the potential applied through diodes 57 and 58 from leads B1 and B2 respectively which are connected to SCRs 13-16 as will become clear from the following description.

Transfer Control Circuit Connections to Data Input Circuits and Multiplication Circuit Refer now to the circuit of SCR 13 and the associated bank of diodes 30-34 which have a common anode connection and which have their cathodes connected to separate circuits as follows. Diode 30 is connected through the output lead 61, also labeled A1, to the data input circuit 79, FIG. 1D. Diode 31 is connected trough a variable resistor 63 and lead 115 to the data input circuit 80, FIG. 1D. The details of the data input circuits 79 and 80 will be described hereinbelow. Diode 32 is connected to lead 91, also labeled B1 to the data input circuit 80. Diode 33 is connected through a variable resistor 93 and leads 116 and 116a (FIG. 1A) to the base tb2 of unijunction transistor 62 in the multiplication portion of the circuit shown in FIG. 1A. A transformer winding T16 is connected across the resistor 93 for purposes to be described. Diode 34 is connected through a variable resistor 95, a diode 96 and leads 118 and 118a to the base 2122 of unijunction transistor 52 in the multiplication circuit of FIG. 1A. The junction of resistor 95 and diode 96 is connected through lead 89 to the units position counting circuit of counters 3116, which counters may be of any suitable known type utilized for counting pulses applied thereto.

Refer now to the circuit of SCR 14 and the associated diodes 70-74 which have a common anode connection and which have their cathodes connected to separate circuits as follows. Diode 70 is connected through lead 64 to the junction of diode 31 and resistor 63 in the circuit of SCR 13. Diode 72 is connected through a variable resistor 147 and leads 116 and 1160 to the base tb2 of unijunction transistor 62, FIG. 1A. A transformer winding T11 is connected in parallel with resistor 147. Diode 72 is connected to lead 161, also labeled A2. Diode 73 is connected through lead 91, also labeled B1, to the data input circuit 80. Diode 74 is connected through a variable resistor 105, diode 106, and leads 118 and 1180 (FIG. 1A) to the base lb 2 of unijunction transistor 52. The junction of resistor 10S and diode 106 is coupled by lead 107 to the tens counting position of the counters 3110.

Likewise, the diodes 110-114 associated with SCR 15 are connected in the circuit as follows. Diode 1111 is connected through lead 64 to resistor 63. Diode 111 is connected to lead 61, also labeled A1; diode 112 is connected through a variable resistor 125, and lead 116 and 1160 to base tb2 of unijunction transistor 62. A transformer winding T12 is connected in parallel with resistor 125. Diode 113 is connected through lead line 92 to the input circuit 80. Diode 114 is connected through a variable resistor 126, a diode 106, and lead lines 118 and 118a to the base [b2 of unijunction transistor 52 (FIG. 1A).

Further, diode 120124 associated with SCR 16 are connected as follows. Diode 120 is connected through lead 64 to resistor 63; diode 121 is connected through lead 92 to input circuit 80; and diode 122 is connected through a variable resistor 127 to lead 116 and 116a to the base tb2 of unijunction transistor 62. A winding T13 is connected in parallel across resistor 127. Diode 123 is connected through lead 161 to the input circuit 79. Diode 124 is connected through a variable resistor 128 and diode 129, leads 118 and 1180 to the base (b2 of unijunction transistor 52. The junction of resistor 128 and diode 129 is connected through lead line 130 to the one hundreds counting position or circuitry of the counters 300.

The operation of the circuit of FIGS. 18' and 1C will be described in detail hereinbelow, in connection with the overall operation of the entire circuitry including the transfer control register of FIG. 18, data input circuits 79, 80 of FIG. 1D and the multiplication circuit of FIG. 1A.

DATA lNPUT CIRCUITS Refer now to FIG. 1D which shows the circuits for receiving the data or input factors that are to be multiplied. As mentioned above, for purposes of this explanation, a number containing two factors (A2, A1) is to be multiplied by another number (B2, B1) also containing two factors. Assume as before that A2 A1=21 and B2 81:29; i.e., the numbers to be multiplied are 21x29. The data input circuit labeled 79 is the input circuit for the factors A2 and A1 and the data input circuit labeled 80 is the input circuit for the factors B2 and B1.

The input circuit 79 includes a pair of switch means or keyboards generally labeled 81 and 82; and, each switch means includes a plurality of interlocked and normally closed contacts numbered 9 which permit any one of the numbers 09 to be entered into the circuit. Each of the switch means 81 and 82 interlocks such that only one of the switch contacts in a given switch can be actuated to an open position during any given time. Thus, a specific digit may be entered into the circuit by actuating switch contact 0-9 in switch means 81 to represent the factor A1, and concurrently another digit may be entered into switch means 82 to represent the factor A2 by actuating its respective switch contacts 09.

Lead 61, which is labeled A1 to represent the factor with which it is associated, is connected from the control registers of FIGS. 18 and 1C to the upper terminal (as oriented in FIG. 1D) of each of the switch contacts l-9 of switch means 81. Likewise, lead 161, which is labeled A2 to represent the factor with which it is associated, is connected from the control registers of FIGS. 18 and 1C to the upper terminal of each of the switch contacts 1-9 of switch means 82. The other or lower terminal of each ofswitch contacts 1-9 of switch means 81 is connected to the lower terminal of the respective switch contacts ll-9 of switch means 82; for example, the lower terminal of switch contact 1 of switch means 81 is connected to the lower terminal of switch contact 1 of switch means 82. Since the individual circuits associated with each of switch contacts 1-9 are similar only the description of one such circuit will be given.

Switch contact 2, for example, of switch means 81 is connected through leads 131 and 131a through two series resistors 132 and 133 to +10 volt potential. The junction of resistors 132 and 133 is connected to the base b of an NPN type transistor T2 which is normally biased to be conducting. The emitter e of transistor T2 is connected to ground reference and the collector c of transistor T2 is connected through a resistor labeled a2 to a +30 volt potential. The transistor T2 functions as an electronic on-off switch. The junction of resistor a2 and collector c of transistor T2 is connected to the anode of a diode 134 whose cathode is connected through leads 117 and 117a to the emitter e of unijunction transistor 52, FIG. 1A; note the circuit path of lead 117 and 117a which is traced from FIG. 1D through FIGS. 1C and 18 to the emitter e of unijunction transistor 52.

The other switch contacts 19 in switch 81 are similarly connected to respective transistor switches. Note also that the switch contact number 0 is not connected to the circuit and hence when switch contact number 0 is actuated, no signal, that is, a zero signal, will be entered to the input circuits 79 and 80.

The operation of data input circuit 79 is as follows. Assuming that the factor A1 is equal to 2, the keyboard of switch means 81 will be actuated to open switch contact number 2. Normally, transistor T2 is biased to be conducting by the current path which may be traced from one of the SCRs 13 or 15 (as will be explained) through lead 61, switch contact number 2 of switch means 81, lead 131, lead 131a, resistor 132 and resistor 133 to l0 volt potential. As long as transistor T2 is conducting, the potential at the junction of resistor a2 and. diode 134 will be at about ground reference. Note that in the assumed condition all the other switch contacts 1 and 3-9 in switch means 81 are closed, hence all the transistors T1, T3- -T9 are conducting, and no signal will be supplied to lead 117.

When switch contact 2 is opened and with SCR 13 or 15 in a conducting state, only transistor T2 will turn OFF. When transistor T2 is OFF, ground potential will be removed from the junction of resistor a2 and diode 134. Accordingly, a current will be permitted to flow from the +30 volt potential through resistor 02, diode 134, lead 117 and lead 117a to charge the capacitor C1 in the circuit of the count unijunction transistor 52, see FIG. 1A. Thus, as will be explained hereinbelow in more detail, a signal representative of the number 2 will be in more detail, a signal representative of the number 2 will be entered into the multiplication circuit. It will be appreciated that each of the resistors a1-a9 in input circuit 79 are weighted in accordance with a selected code, in this case a digital code, to electrically represent the desired number. For example, the resistor a1 may be 9 times larger than resistor a9; thus, capacitor C1 will charge only one-ninth as rapidly when resistor 01 is effectively in the circuit as compared to its charging rate when resistor a9 is in the circuit.

The operation of switch means 82 of the data input circuit 79 of FIG. 1D when an A2 signal is coupled through lead 161 to switch means 82 is similar to the operation of the switch means 81 when an A1 signal is coupled through lead 61.

Refer now to input circuit 80, the data input circuit for-factors B2 and B1. Input circuit includes a pair of switch means or keyboards generally labeled 83 and 84; each switch means 83 and 84 includes a plurality of interlocked and normally open contacts numbered 0-9 which permit any one of the numbers 09 to be entered into the particular circuit. Each of the switch means 83 and 84 interlock such that only one of the switch contacts in a given switch can be actuated to a closed position during any given time. Thus, a specific digit may be entered into the circuit in switch means 83 to represent the factor B1 and another digit may concurrently be entered into switch means 84 to represent the factor B2 by ac tuating respective switch contacts 09. Leads 91 and 92, also labeled B1 and B2 to represent the factor with which they are associated, are respectively coupled in common to the upper terminal (as oriented in FIG. ID) of the normally open switch contacts 1-9 of switch means 83 and 84 in the input circuit 80. The other or lower terminal of each of switch contacts 1- -9 of switch means 83 is connected directly to the lower terminal of the respective switch contact 1-9 of switch means 84; for example, the lower terminal of switch contact 1 of switch means 83 is connected to the lower terminal of switch contact 1 of switch means 84. The lower terminal of each of switch contacts 19 of switch means 83 and 84 is connected lll through a resistor to the base of an associated transistor; for example, the lower terminal of switch contact 2 is connected through resistor 1136 to the base b of transistor S2, as will be described. Since each of the individual circuits in the input circuit 60 are similar, only the circuit of switch contact 2 of switch means 34 will be described in detail. Lead 92 is coupled to the upper terminal (as oriented in FIG. 11)) of normally open switch contact 2 in switch means 34 and the lower terminal of switch contact 2 is connected through two series resistors i136 and 137 to volt potential. The junction of resistors 1136 and 137 is connected to the base b of an NIN transistor S2; transistor S2 is biased to be normally nonconducting. When switch contact 2 of switch means 34 is closed a potential will be supplied through SCR H5 or SCR 16 (as will be explained), diode H3 or diode T21, lead 92, switch contact 2, and resistors T36 and 137 to bias transistor S2 to conduction. When transistor S2 conducts, a circuit path will be completed from 8+ potential through the conducting one of SCR I5 or SCR l6, diode H0 or diode 120, lead 64, resistor 63, lead 115, lead llSb, capacitor b2 and transistor S2 to ground reference. Capacitor b2 will then charge through the aforetraced circuit path toward a positive potential.

Note that lead lllSb is also connected through lead 115 and lead llllSa (FIG. 11A) to the emitter e of unijunction transistor 62. Thus, each of the capacitors bll...b9 and the associated transistors SI...S9 are connected in parallel with the emitter e to the base tbl path of unijunction transistor 62. The circuit is arranged such that as the energized one of the capacitors bl...b9 charges toward a positive potential, the avalanche point of the unijunction transistor 62 will be reached at a given point on the charging curve of said energized capacitor to cause the unijunction transistor 62 to fire.

As will be readily appreciated, the size of capacitors bl...b9 are electrically weighted corresponding to the number which they are to represent in the multiplication circuit. For example, capacitor b2 will have a capacitive value twice as large as capacitor bl and hence b2 will take twice as long to charge to the avalanche point of unijunction transistor 62.

MULTIPLICATION BY ZERO The operation of the circuit when the number ll is to be entered to represent a factor in the multiplication will now be described. This is of interest when a zero is a factor in the multiplication, for example, in the multiplication of factors such as 2l 20 or x40, etc.

Refer first to the data input circuit 79. The operation of the entry of 0 for either factor A1 or A2 is similar; hence the description of the circuit will be given in the case wherein zero is to be entered in switch means 81 to represent the factor AI. When the zero is entered into switch means or keyboard 81, the switch contact number i) is opened. When this occurs, all the other switch contacts ll-9 in switch means fill will be closed. Thus, all the transistors T1...T9 will be biased to conduct; accordingly, the collectors c of transistors T1 ...T9 will be at essentially ground potential. The junction of resistors all...a9 and the associated diodes will be at essentially ground potential and no signal will thus be coupled to lead i117 and lead llll7a to charge the count capacitor C1 in the circuit of unijunction transistor 52. Thus zero or no counts will be entered into the circuit during a given time base provided by the operation of data input circuit 79.

Refer now to data input means 80 and switch means 83 and 84. The operation of the circuit when factor Bl=0 is similar to the operation of the circuit when B2=0; hence, an explanation will be given only with respect to the case when Bl==0. When one of contacts 1-9 in switch means 83 is closed, and the BI lead 911 has a high potential applied thereto from the B-iline through the conducting one of SCR H3 or SCR M, diode 32 or diode 73, a high potential will be coupled through the closed switch contact and a respective diode generally labeled 133, and resistors M1 and 1412 to the l0 volt potential line to bias NPN transistor M0 to conduction. Transistor M0 includes a base b connected to the junction ofresistor MT and M2, an emitter e connected to ground, and a collector c connected through a resistor 143 to +30 volt potential. As long as transistor M0 is conducting, its collector c will be at essentially zero potential.

However, when switch contact number 0, representing the entry of a factor Bll=0, is closed, all of the other switch contacts 1-9 will be opened. When all the switch contacts ll--9 are open, transistor M0 will no longer be forward-biased and will turn OFF, and the potential at its collector c will rise to a high level at terminal 149.

The high potential at terminal 149 will cause transistor 1435 to conduct. Transistor 1415 which is of the NPN type, has its base b connected through resistor 1436 to terminal 149, and through another resistor 147 to -10 volt potential. The

emitter e of transistor M5 is connected to ground, and its collector c is connected through a capacitor M8 to lead 1115b.

When transistor 1145 conducts, the capacitor 148 will start to charge toward a positive potential through a circuit which may be traced from the energized one of the SCRs l3l6; the respective diodes 31, 70, or I20, lead 641, resistor 63, lead Ills, lead b, capacitor M8 and the collector c to emitter e electrodes of transistor I45 to ground reference. When the capacitor M8 reaches the avalanche point of unijunction transistor 62, transistor 62 will conduct and cause the transfer control registers of FIGS. 1B and EC to operate to shift its control position from one SCR to the succeeding SCR which, as will be explained, causes a shift to initiate the multiplication of factors in a higher order position which corresponds to a multiplication by zero. Capacitor 148 is a relatively small capacitor and is charged or reaches the avalanche point of unijunction transistor 62 rather rapidly to provide a rapid shift or multiplication by zero in response to a zero digit input.

Note also that the high potential at terminal 149 will be coupled through zero control lead l5! (see the circuit path of lead 151 through FIGS. TD, IC, 18 and 1A) to the base b of transistor W8 to bias transistor 188 to conduct. As long as transistor W8 is conducting, the count capacitor C1 cannot charge to provide any count pulses and will remain at essentially ground potential. Thus, the zero control circuit including transistors M0 and 1145 will concurrently do two things; it will prevent the count capacitor C1 from charging, and will also cause the transfer control register of FIGS. 18 and 1G to shift or step.

OPERATION The operation of the overall multiplication circuit of FIGS. 11A, 113, 1C and 11D will now be explained. To initiate the operation of the circuit, the switch 12 for energizing the overall system is closed. As explained above, the Rest Control circuit SCR 1.7 will be turned ON when switch 12 is closed. The numbers representative of the input factors Al, A2, and the numbers representative of the input factors El, B2 are respectively entered into the switch means 81, 82, 83 and 841. Again, assume the number 21 is to be multiplied by the number 29; i.e., (A2 AI) (B2 Bl)=(2l (29). Next, the start pushbutton l8 (FIG. 1C) is closed to complete an electrical circuit to bias transistor 19 to turn ON. When transistor 119 is ON a current will be permitted to flow in the primary winding WI of transformer 24, which in turn develops and couples a signal to the gate electrode 3 of SCR 113 to cause SCR E3 to turn ON.

When SCR 13 turns ON, its cathode 0 will rise to a relatively high (toward B+) potential and this high potential is coupled through lead 4.0 to the capacitor 55 of the Rest Control SCR 117. Since the potential of capacitor 55 cannot change instantaneously, this voltage is coupled through diode 2611 and resistor 262 to the cathode c of SCR 17 causing a momentary reverse current to flow through SCR 17 to turn SCR I7 OFF. Note also that the high potential at the cathode c of SCR t3 charges the commutating capacitor 3% to approximately 3+ potential through resistor 39.

The voltage at the cathode of SCR 13 will be coupled through each of the diodes 30, 31, 32, 33 and 34 to the respective circuits previously traced. A signal is coupled'through diode 30 and lead 61 to the switch means 81. Since switch contact 1 in switch 81 has been activated to open to indicate the entry of the number l into the circuit as the factor Al, the potential at the base b of transistor T1 will be removed and transistor T1 will be turned OFF. Accordingly, a signal will be permitted to flow from +30 volt potential through the resistor a1, diode 134a, lead 117, and lead 1170 to charge capacitor C1 in the count unijunction transistor circuit 52, (see FIGS. 1D,1C,1B and 1A).

As mentioned above, the resistive value of resistor a1 is weighted to indicate the number 1; and, more specifically, resistor all is weighted to permit capacitor C1 to charge once during a given unit value of time. Capacitor C1 will thus charge through the foregoing circuit toward the positive +30 volt potential at a rate determined by the resistance a1. Each time capacitor C1 is charged to the avalanche point of unijunction transistor 52, the unijunction transistor will fire or become conductive. When this occurs a current path will be completed to permit current flow from the B+ potential line through SCR 13 (FIG. 1C), diode 34, resistor 95, diode 96, lead 118 (FIGS. 1C and 18), lead 1184 (FIG. 1A), and the base tb2 to base tbll electrodes of unijunction transistor 52 to ground. Accordingly, a potential change or pulse will occur at the junction of resistor 95 and diode 96 (FIG. 1C) which pulse is coupled through lead 89 (FlGS. 1C and 18) to the units counting position of the counter 300.

Concurrently with the foregoing operation, and since the switch contact number 9 in data input circuit 84 has been closed to indicate the entry of a factor Bl=9, a voltage will be coupled through SCR 13, diode 34, lead 91, closed switch contact 9, and series resistors 144 and 150 to bias transistor S9 to turn ON. When transistor S9 turns ON it will permit the associated capacitor b9 to charge through the circuit which can be traced from conducting SCR 13, diode 31, variable resistor 63, lead 115, lead 115b, capacitor b9 and transistor S9 to ground reference. Capacitor b9 is relatively weighted to charge to the avalanche point of unijunction transistor 62 in a period of time to indicate the number 9.

As mentioned above, lead 115b is also connected through lead 115 and lead 115a to the emitter e of unijunction transistor 62, and hence capacitors b1...b9 are connected in parallel with the emitter e to base tbl of unijunction transistor 62. Accordingly, unijunction transistor 62 will be caused to avalanche ata point in time which is a function of the charging rate and hence of the value of capacitor b9. Since b9 is weighted to indicate a value of nine unit values of time, it will take capacitor b9 nine unit values of time to charge to a point at which the time unijunction transistor 62 will fire. In this example, during the nine unit values of time, the other or count unijunction transistor 52 will fire a total of nine times, that is, once during each unit value oftime.

When the time unijunction transistor 62 fires, a circuit will be completed from B+ potential through conducting SCR 13, diode 33, variable resistor 93, lead 116, lead 116a, and the base 2172 to base {111 circuit path of unijunction transistor 62 to ground reference. The current flow through resistor 93 will energize the primary winding T10 connected in parallel with resistor 93. Primary winding T10 is connected to inductively energize winding T10A in the circuit of SCR 14 to cause a biasing current to flow from the gate 3 to the cathode c electrodes of the SCR 14, and cause SCR 14 to tire or become conductive. When SCR l4 fires, the voltage at the cathode c of SCR 114 will rise to approximately B+ potential, and this voltage will be coupled to capacitor 38. Since the charge across capacitor 38 cannot change instantaneously, a voltage of approximately twice B+ potential will tend to be coupled through diode 37, and resistor 36 to the cathode of SCR 13, thus, momentarily rising the potential at the cathode of SCR 113 and causing a momentary reverse current to flow through SCR 13 which causes SCR 13 to turn OFF.

The overall effect is to cause the circuit to provide nine output pulses on lead 89 to counters 300; i.e., one pulse for each one of the nine unit values of time, and to cause the transfer control register to step through and shift the circuit, from one count position to the next higher order. count position to initiate the multiplication of the second group of data, namely A2 B1. Note that the number of pulses coupled to the counters 300 is dependent on the number of times which unijunction transistor 52 is caused to conduct and is dependent on the number of times capacitor C1 cycles representative of the particular A input factor during a given time period representing the particular B input factor.

The firing of SCR 14 now sets up the circuits to perform the multiplication of the factors A2XB1 through the circuits of diodes 70-74 previously traced. In this case A2 B1=2X9. Note that the capacitor b9 representative of factor B1 is again energized through the circuit including SCR 14, diode 73, lead 91, switch contact 9, capacitor b9 and the transistor S9.

With SCR 14 energized, the programming of the circuit is such that the resistor a2 representative of factor A2 is now energized or effectively coupled into the circuit. With switch contact 2 being open and all the other switch contacts 1 and 3- -9 being closed, the current path traced from SCR 14, diode 72 and lead 161 to the parallel connected switch contacts 0, l and 3-9 will maintain the associated transistors T1 and T3- -T9 (indicated by the dotted lines) in a conducting state thus coupling no signal to lead 117. However, since switch contact 2 in switch 82 is open, transistor T2 will be cut off and remove ground potential from the junction of resistor a2 and diode 134. Accordingly, a current path will be completed from +30 volt potential line (FlG. 1D) through resistor 02, diode 134, lead 117, (FlGS. 1D, 1C, 13) and lead 117a (FIG. 1A) to charge capacitor C1 in the circuit of count unijunction transistor 52. Capacitor C1 will charge to the avalanche point of unijunction transistor 52 twice during each unit value of time and accordingly unijunction transistor 52 will fire twice during each unit value of time and will fire 18 times in nine unit values of time to represent A2 B1=2X9=l 8. This multiplication thus becomes the second term of the above equation l and the numerical example of(2l X29) cited above.

With SCR 14 conducting each time that unijunction transistor 52 fires a circuit path will be completed from B-lpotential, SCR l4, diode 74, resistor 105, diode 106, lead 118, lead 118a, and the base tb2 to base tbl of unijunction transistor 52 to ground. A potential change or pulse will result at the junction of resistor and diode 106 which pulse is coupled through lead 107 to the tens counting position of the counters 300.

The avalanching of unijunction transistor 62 after the B1 or 9 (in this example) unit value of time produces a pulse in the primary winding of transformer T11 which energizes secondary winding T11A and turns on SCR 15. When SCR 15 turns ON, SCR 14 is turned OFF in the similar manner as previously described for turning SCR 13 OFF.

Circuits to the unijunction transistors 52 and 62 are now completed through SCR 15 and the diodes 110114 similarly as in the case of SCRs 13 and 14. The factors to be multiplied are A1 and B2 and' the output pulses are again coupled through lead 107 to the tens decimal position. Note that the resistor 126 associated with SCR 15 and resistor 105 associated with SCR 14 have their lower terminals connected in common to the anode of diode 106 and to lead 107.

Upon completion of the multiplication (A1XB2) SCR 16 will turn ON causing SCR 15 to turn OFF in the manner previously explained. Circuits to the transistors 52 and 62 are now completed through SCR 16 and diodes -124 and factors A2 and B2 are effective in the circuit. The output pulses are coupled through lead 130 to the hundreds decimal position of the associated counters 300. Note that the counters 300 may be of any suitable known type arranged to count input pulses and to provide the carry operation from one order position to the next higher order position. A number of such counters are available commercially.

After the multiplication of AZXBZ is completed, the firing of unnunction transistor 62 causes SCR 17 the Rest Control SCR. to turn ON and turn SCR 16 OFF The circuit is now in condition to initiate the multiplication of other additional numbers or factors The completed multiplication. as described above. can be shown in chart form as fOllOWSl ands lrcds Tens (nits First t n-ration \.\1x I11 1 1th:

Entt-rml in units column. .1

Second Operation (Al x B2) (1x 2)' Entered in tens column.-.

Subtotal to hundreds column. 1 8

Subtotal..... :2 O 9 Fourth Operation (A2 x B2) (2 x 2 Entered in hundreds column and added 4-4 Total number of counts 6 0 9 Assuming a unit time of 90 microseconds, the total time required for the multiplication of 21 X29 is 1980 microseconds as shown in the chart of FIG. 2.

Utilizing the method and apparatus of the present invention, each multiplication of 9X9 requires (9X90)=8l0 microseconds. In the invention, to multiply 2 digits by 2 digits a total of 4 multiplications are required; accordingly, to multiply 99x99 requires 90 9X4=3240 microseconds which is many times faster than the time required to multiply 99 99 when utilizing a unit pulsevalue assignment.

Also, the circuit of FIG. 1 provides a high degree of accuracy by resorting to or operating on a small field of (9X9); i.e., the highest individual multiplication which has to be performed by the circuit of FIG. l is the multiplication of 9X9.

It should be noted that there is no theoretical limit to the digits which can be multiplied. Thus, stages similar to those shown above could be connected in the circuit to multiply All...Ari by B1...Bn and combinations thereof. Further, there is no restriction to the sequence of performing the multiplications. For example, the answer would be the same if the (A2XB2) multiplication were performed first. Also, it is possible to group the multiplicand and multiplier in different configurations; for example, assume a four factor number A4, A3, A2, A1 is to be multiplied by a two factor number B2, B1, as follows:

for example: 7965 2.- i 37 The foregoing can be grouped thus by:

where u v and w are two digit numbers as illustrated above. The multiplication may now be arranged as shown below:

and the multiplication is performed as;

(wXv)+(w u)(lOO)=pr0duct Eq. (A)

(37X65)+(37X79)( l0O)=product thus,

(2405)-H292300)=294705. In the present example, the product Of(WXl') in pulses is fed to the units counter and the product (wXv) is fed to the hun- This grouping can be arranged as A A,=v and may be performed by:

where v is again a two digit number.

In the present embodiment of the in invention resistors al...a9 a9 are connected to the count unijunction transistor 52 and capacitors bl...b9 are connected to the time unijunction transistor 62 representative of input factors. However it should be noted that any combination of the resistive and capacitive components may be utilized as the input factors; for example, factors A,, A can be represented by capacitors and factors B,, B can be represented by resistors.

Also, it should be understood that while a digital code is used herein for the entry of input data, any combination or coded arrangement could thus be employed. In the present embodiment, for example, four capacitors or resistors could be employed in various combinations of the components and arranged to be energized in a binary coded decimal code to provide a desired output as is well-known in the art.

COMPENSATION CIRCUITS For certain applications it has been found desirable to improve the accuracy of the circuit of FIG. 1A without adding the entire circuit portion 200. Such improvement may be obtained by compensating for the pulse discharge time of the capacitors as will be explained. For purposes of this explanation and referring to FIGS. 4 and 5, the time capacitors representative of capacitors al...a9 in FIG. ID will be designated generally As C2.

One cycle of the counting capacitor C1 consists of its charge time t and its discharge time r Assume that the factors of the circuits are precisely set so that during the duration of waveform 332 in FIG. 6, there are exactly 9 charge times and 9 discharge times represented by the waveform 333. Assume the discharge time (t,,) of waveform e of FIG. 6 (which is shown considerably exaggerated for purposes of explanation) is a significant part of the entire capacitor cycle comprising both its charge and discharge time (z +t Assume the cycle of the count circuit Cl is now changed, such as by changing the resistance value of the associated resistor. It will be readily seen that if the charging and discharging waveforms are displaced from the ideal waveform 333 as shown by the dotted waveform 334 the time for the completion of discharge of, say, the ninth cycle of FIG. 6, may deviate sufficiently so that less than 9 complete cycles of the count capacitor C1 will be obtained. If the time represented by I is an appreciable part of the total time (t,.+t as has been assumed, the total deviation under certain conditions may exceed one count.

' The foregoing condition may be corrected by making changes to reduce the discharge time of the count capacitor Cl such as by connecting a transistor to the capacitor Cl and the unijunction transistor 52 as shown in FIG. 41 wherein like numbers refer to like elements in FIG. 1A. In FIG. 4, an NPN transistor 301 has its collector connected to the emitter e of unijunction transistor 52, its base b connected to the base tbl of transistor 52 and its emitter e connected through a biasing diode 302 to ground. A resistor 304 is connected from base tbl of unijunction transistor 52 to ground. When the potential on capacitor C1 increases to the avalanche point of unijunction transistor 52, the transistor 52 conducts and discharges capacitor C1 through the emitter e to base tbl path of unijunction transistor 52, and resistor 304 to ground. When unijunction transistor 52 conducts, transitor 301 will be biased to conduct and thus provide a low resistance path for capacitor C1 to discharge through a path traceable from the upper plate of C! through the collector c to emitter e path of transistor 301. Capacitor C1 will thus discharge quickly, and decrease the time duration 1,, to a minimum.

Another means of correcting for the foregoing condition wherein the discharge time r may adversely affect the operation of the circuit of FIG. LA by the circuit of FIG. 5. This second alternative way of increasing the accuracy of the system provides a means of holding the charge of the time capacitor C2 constant during the discharge time 1,, of capacitor Cl, as shown in H0. 6. Accordingly, an element of time equal to 1,, is removed from the charging rate of the time capacitor C2 for every single cycle or count of capacitor C1. Note that the total error due to the discharge time of Cl is proportional to the number of discharge times multiplied by the length of the discharge time. Thus, by modifying, that is, increasing the time base by an amount proportional to the discharge time the accuracy of the system is improved.

The circuit of HO. 5 provides the compensation for the discharge time I In FIG. 5, wherein like numbers refer to like elements in FIG. 1A, the circuits includes an NPN transistor 306 having its collector c connected to the anode of a diode 307 whose cathode is connected to the upper plate of the time capacitor C2 and to the emitter e of unijunction transistor 62. The anode of diode 307 and the collector c of transitor 306 are connected through a resistor 63 to the 13+ potential line. The emitter eof the transistor 306 is connected to ground, and its base b is connected through a lead 308 to the base tbl of unijunction resistors 52.

The operation of the circuit is as follows. When the count capacitor C1 charges to the avalanche point of unijunction transistor 52, transistor 52 fires. A current will now flow from the 13+ line through resistor 95, diode 96, the base lb2 to the base tbi of unijunction transistor 52 through lead 308, and the base b to emitter e electrodes of transistor 306 causing transistor 306 to conduct. When transistor 306 conducts, diode 307 is back biased and capacitor C2 cannot charge during the time the capacitor C1 is discharging through unijunc tion transistor 52. When the capacitor C1 is completely discharged, the transistor 306 will turn OFF and permit capacitor C1 to resume its charging rate. Thus, the charge on capacitor C2, through the action of diode 307, is maintained at a given level during the discharge time r of capacitor C1 and compensates for any variations in the discharge time t,, of capacitor C 1.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

We claim:

1. A circuit for performing multiplication comprising:

a multiplier for receiving signals representative of factors to be multiplied and providing a pulsed output representative of the product of said factors;

a plurality of control registers connected to said multiplier for programming the multiplication of said factors in selected groupings;

a. said control registers are arranged in serial association and each comprises an electronic switching means;

b. means for turning on or closing a first of said electronic switching means to couple an enabling potential to said mutiplying circuit; and

c. inductive means associated with each control register and arranged to be energized when a multiplication operation is terminated, and an energized inductive means in one register causing an electronic switching means in the succeeding register to be turned ON.

2. A circuit for performing multiplication wherein:

a multiplier for receiving signals representative of factors to be multiplied and providing a pulsed output representative of the product of said factors;

a plurality of control registers connected to said multiplier for programming the multiplication of said factors in selected groupings;

a. said multiplier performing a multiplication operation of selected factors when a given control register is energized;

b. said multiplier including means for energizing a succeeding control register when said given operation is terminated; and

c. means for deenergizing said given control register in response to the energizing of said succeeding control register.

3. A circuit for performing multiplication comprising, in

combination:

a. a multiplier for multiplying numerical data consisting of more than two input factors, and said multiplier providing a pulsed output representative of the results of the multiplication;

b. input means coupling factors comprising time length multiples of a selected unit value of time representative of numerical data to be multiplied by said multiplier;

c. a plurality of control registers connected to said input means and to said multiplier for controlling the multiplication of said data in selected groups; and

d. transfer means for said registers for transferring control from one register to a succeeding register upon the completion of a multiplication operation of one group of factors and initiating the multiplication of another group of factors.

4. A circuit for performing multiplication comprising:

a multiplier for multiplying numerical data consisting of more than two input factors, and said multiplier providing a pulse output representative of the results of the multiplication;

input means for coupling the factors to be multiplied to said multiplier;

a plurality of control registers connected to said input means and to said multiplier for controlling the multiplication of said data in selected groups;

transfer means for said register for transferring control from one register to a succeeding register upon the completion of a multiplication operation of one group of factors and initiating the multiplication of another group of factors;

a. counter means for counting and summing pulses; and

b. output means for connecting the output pulses from said multiplier to said counter in selected numerical order positions, whereby the pulses may be summed to obtain the product of said input factors.

5. A circuit as in claim 4 wherein the output pulses which result from the multiplication of a given grouping of factors are selectively coupled to selected numerical order positions in said counter to enable the summation of the various multiplication operations to provide the product of the numerical data coupled to said circuit.

6. A circuit for performing multiplication comprising:

a multiplier for multiplying numerical data consisting of more than two input factors, and said multiplier providing a pulsed output representative of the results of the multiplication;

input means for coupling the factors to be multiplied to said multiplier;

a plurality of control registers connected to said input means and to said multiplier for controlling the multiplication of said data in selected groups;

a. said control registers each comprising electrical circuitry including an SCR having an anode, a gate, and cathode electrodes;

b. capacitive means connected to the circuit of the cathode of each of said SCRs;

c. means for turning on a first of said SClRs whereby the potential at its cathode rises to a high potential and said capacitor charges to the potential at said cathode;

d. inductive means associated with each of said SClRs being connected to be energized when a multiplication operation is terminated, and said inductive means when energized turning on a succeeding SCR;

I e. means connecting a given SCR to a preceding SCR, said given SCR when on causing the potential at the cathode of said preceding SCR to rise to approximately twice the potential at the anode of said preceding SCR to thereby cause a momentary reverse current to flow through said preceding SCR to turn said preceding SCR off; and

transfer means for said registers for transferring control from one register to a succeeding register upon the completion of a multiplication operation of one group of factors and initiating the multiplication of another group of factors.

7. A circuit for performing multiplication comprising:

a multiplier for receiving signals representative of factors to be multiplied and providing a pulsed output representative of the product of said factors;

a. said multiplier including capacitive means associated with a first unijunction transistor and arranged to provide a time base which is a multiple ofa selected basic unit value of time, and of a length representative of a given input factor, and a second capacitive means associated with a second unijunction transistor and arranged to provide a number of pulses during each unit value of time to represent a second given input factor;

b. multivibrator means for providing a time delay between multiplication operations;

c. means for changing the charge across said capacitors to a selected potential after the operation of each multiplica- Zlli ing the operation of said capacitors comprises:

a. a unijunction transistor having an emitter and two base electrodes;

b. a capacitor and resistor connected in series, and the emitter being connected to the junction of said resistor and capacitor;

c. means for adjusting said resistor and capacitor to cause said unijunction transistor to fire at intervals representative of the basic unit value of time; and

d. means connecting said unijunction transistor to said pulse providing capacitor, whereby each time said unijunction transistor fires indicating a unit time value said count capacitor is discharged to zero.

9. A circuit as in claim 8 wherein:

a. the unijunction transistor associated with said time base capacitor provides a first signal to energize said control register at the termination of each time base, said unijunctiontransistor concurrently providing a second signal to discharge said capacitor in said synchronizing circuit, said count capacitor, and said time base capacitor; and said unijunction transistor concurrently providing a third signal to said time delay multivibrator to delay the initiation of the next multiplication operation.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No- 3,588,479 Dated June 28, 1971 lnventol-(s) Robert M. Henderson et al It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 1, line 73 cancel "and", first occurrence; column 2, line 64, "52 should read k5 column 3, line 43, "228 to 30" should read 228 to +30 ---5 column line 36, "drop essentially" should read drop to essentially column 7, line 68, "of" should read for column 8, line 61, "72" should read 71 column 9, line 5, "92" should read 91 line 9, "diode" should read diodes column 10, line 38, cancel "in more detail, a signal renresentative of the number 2"; line 39, cancel "will be column 11, line 32, "of said" should read of the said column 16, line 19, cancel "in"; line 20, cancel "a9", second occurrence; line 52 "to" should read td column 17, line ll, "1A by" should read 1A is by line 32, "eof" should be e of line 34, "resistors" should read resistor Signed and sealed this 12th day of December 1972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOT'ISCHALK Attesting Officer Commissioner of Patents FORM po'wso nosg) USCOMM-DC scan-Pas b l) S GOVERNMENT PRINTHG OFFICE: 1919 0-36i-534, 

